AR# 66347

UltraScale FPGA Gen3 Integrated Block for PCI Express v4.1 Rev1 (Vivado 2015.4) - ASPM Support Update


Version Found: 4.1 (Rev1)

Version Resolved and other Known Issues: (Xilinx Answer 57945)

The following ASPM support update has been added in the patch attached with this Answer Record.

Gen3 Speed:

No ASPM : Yes
ASPM L0s : No
ASPM L1 : Yes
Simultaneous L0s and L1 : No

Gen1/Gen2 Speed:

No ASPM : Yes
ASPM L0s : Yes
ASPM L1 : Yes
SimultaneousL0s and L1 : No

The above ASPM options are selectable in the 'Power Management' tab with 'Advanced' mode in the core configuration GUI.

This article is part of the PCI Express Solution Centre
(Xilinx Answer 34536) Xilinx Solution Center for PCI Express


Please follow the instructions below to install the patch:

  • The provided patch is for Vivado 2015.4
  • Unzip the attached zip file to the directory of your choice.
  • Open Vivado 2015.4 and create a new project.
  • Open IP catalog. Right click the core you are using and choose IP Settings.
  • Click Repository Manager and point it to the location where you have unzipped the patch.
  • Click OK and you are now ready to generate the core.
  • If you have previously generated the core, you can choose 'Upgrade IP' on your core.
  • Alternatively, you can use the MYVIVADO environment variable and point this to the location of the patch.

Note: The ASPM update in the patch will be integrated in a future release of the core.

Revision History:

15/1/2016 - Initial Release


Associated Attachments

Name File Size File Type 819 KB ZIP
AR# 66347
Date 01/18/2016
Status Active
Type Known Issues