AR# 66354

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JESD204 Solution Center - Design Assistant - General Debug Tips

Description

This Answer Record should be used as a starting point when debugging general issues with the JESD204B / JESD204C cores and the JESD204 PHY.

Solution

General Information to be gathered that helps with Debugging

  • What version of the core is being used?

  • What type of behavior is being seen?
  • Is this issue seen in hardware, simulation, or both?
  • Does the design include JESD RX, JESD TX, both, and / or JESD PHY?
  • Is a block diagram of the design available?
  • What data rate is the design running at?
  • What is the refclk and core clock frequency?
  • What Subclass is being used?

Files that are useful for Debug:

  • XCI file(s)
  • IP Integrator design or Tcl file that regenerates the design easily
  • Simulation or hardware capture of the error

Parameter Basics:

M = number of converters

N = resolution of the converter

i.e Quad channel ADC with a resolution of 14: M = 4; N = 14

N' = number of nibbles (calculated by dividing N by 4)

L = number of lanes

Lane Rate = (M x S x N' x 10/8 x FC) / L

F = (M x S x N') / (8 x L)

Losing Synch:

The core will assert SYNC for the following reasons:

Full (long) re-sync request:

  • 4 consecutive bit errors (disparity or notintable errors)
  • 4 consecutive unexpected Kx.y characters (rxcharisk expected only at the end of the frame)
  • 8 consecutive misalignment errors (multiframes not aligned)

Short SYNC error report (only if enable error reporting by SYNC config bit set in the Error Reporting RX register 0x034) is triggered when a single bit error or unexpected Kx.y character is received.

Gigabit Transceivers:

For link issues related to the GTs, please start with the HSSIO Design Assistant Debugging page.

This is a good starting point to step through the different steps to get a clean working transceiver.

(Xilinx Answer 57237)Xilinx HSSIO Solution Center - Design Assistant Serial Transceiver Debugging

Clocking

The clocking scheme chosen is very important for JESD204 link success. PG066 JESD204 Product Guide includes the recommended Clocking Schemes that should be used.

It is strongly recommended that you use one of the clocking schemes presented in this section. Use of alternative clocking schemes may lead to design failure.

If there are issues with the link coming up, check the lock signals of the MMCM or GTs (QPLL / CPLL).

When in Subclass 1 mode, SYSREF signal must be generated synchronous to the core clock and should be driven from an external device generating SYSREF for both TX and RX.

In some circumstances, it can be advantageous to use the same clock frequency or source for both core clock and reference clock. However this might not always be practical.

It is important to understand the limitations imposed on the reference clock and core clock, together with system-level implications such as the synchronous capture of SYSREF / SYNC for Subclass 1 or 2 deterministic latency. 

The Clocking section of PG066 should be consulted for further details.

Reset

Understanding what resets are used with the JESD204 core can allow you to develop your system correctly.

  • System Reset is an asynchronous reset that will reset the complete system (core logic and transceiver) - this is tx_reset on a transmit core and rx_reset on a receiver core.
    The AXI4-Lite interface and configuration registers are unaffected by these reset signals.
  • s_axi_aresetn is a separate reset signal that is provided for the AXI4-Lite interface which resets the configuration registers to the default values.
    The AXI core should be reset whenever changes are made to core parameters.
  • Software Reset is a register provided through the AXI4-Lite interface which triggers a data path reset sequence for a transmit or receive logic data path under software control.
    The configuration registers are unaffected by this operation. The use of this reset does not reset the PLLs.
  • Watchdog Timer Reset acts in the same manner as the Software Reset. The Watchdog timer can be disabled, if necessary, using a register access.
    In normal system operation, Xilinx recommends that the Watchdog remain enabled. For more information, consult the Watchdog Time Reset section of PG066.
  • AXI4-Stream Reset - when either a System Reset or Software Reset is performed, the rx_aresetn or tx_aresetn outputs are asserted Low until the reset cycle is completed.

(Xilinx Answer 66901)JESD204 - Reset settings


Deterministic Latency:

Please consult the Latency calculation checklist and (PG066) sections on Deterministic Latency for more information.

(Xilinx Answer 66143)IP JESD204 - Latency calculations checklist
(Xilinx Answer 67442)JESD204B - A simplified approach to achieving robust repeatable latency


Debug Signals:

(Xilinx Answer 66916)Debug signals

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
67695 JESD204 - Design Assistant N/A N/A

Child Answer Records

AR# 66354
Date 10/25/2017
Status Active
Type Solution Center
IP
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