General Information to be gathered that helps with Debugging
Files that are useful for Debug:
M = number of converters
N = resolution of the converter
i.e Quad channel ADC with a resolution of 14: M = 4; N = 14
N' = number of nibbles (calculated by dividing N by 4)
L = number of lanes
Lane Rate = (M x S x N' x 10/8 x FC) / L
F = (M x S x N') / (8 x L)
The core will assert SYNC for the following reasons:
Full (long) re-sync request:
Short SYNC error report (only if enable error reporting by SYNC config bit set in the Error Reporting RX register 0x034) is triggered when a single bit error or unexpected Kx.y character is received.
For link issues related to the GTs, please start with the HSSIO Design Assistant Debugging page.
This is a good starting point to step through the different steps to get a clean working transceiver.
|(Xilinx Answer 57237)||Xilinx HSSIO Solution Center - Design Assistant Serial Transceiver Debugging|
The clocking scheme chosen is very important for JESD204 link success. PG066 JESD204 Product Guide includes the recommended Clocking Schemes that should be used.
It is strongly recommended that you use one of the clocking schemes presented in this section. Use of alternative clocking schemes may lead to design failure.
If there are issues with the link coming up, check the lock signals of the MMCM or GTs (QPLL / CPLL).
When in Subclass 1 mode, SYSREF signal must be generated synchronous to the core clock and should be driven from an external device generating SYSREF for both TX and RX.
In some circumstances, it can be advantageous to use the same clock frequency or source for both core clock and reference clock. However this might not always be practical.
It is important to understand the limitations imposed on the reference clock and core clock, together with system-level implications such as the synchronous capture of SYSREF / SYNC for Subclass 1 or 2 deterministic latency.
The Clocking section of PG066 should be consulted for further details.
Understanding what resets are used with the JESD204 core can allow you to develop your system correctly.
|(Xilinx Answer 66901)||JESD204 - Reset settings|
|(Xilinx Answer 66143)||IP JESD204 - Latency calculations checklist |
|(Xilinx Answer 67442)||JESD204B - A simplified approach to achieving robust repeatable latency|
|(Xilinx Answer 66916)||Debug signals|