Version Found: 2015.3
The DELAY_VALUE is not correctly set within the synthesized netlist. This will affect the RX_BITSLICE, TX_BITSLICE, and RXTX_BITSLICE.
Note: this Answer Record should not be viewed in isolation.
For all other known issues and to see what version of Vivado / High Speed SelectIO Wizard these issues have been resolved in, please refer to (Xilinx Answer 64216)
This issue is resolved in version 3.0 of the High Speed SelectIO Wizard, included in the 2016.1 release.
In older versions the DELAY_VALUE can be manually overridden by using constraints with the synthesized netlist.
Alternatively the user can edit the HDL file in the following location, following the flow described in (Xilinx Answer 57546):
The following 3 files need to be edited and can be found in the following directory:
If necessary, the edited IP can be packaged up and re-used. For more information see (UG1118).