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AR# 66462

2016.3 Vivado Power Optimization - UltraScale Read Address Change Issue with Initialized block RAM

Description

Under rare circumstances, it is possible that the initial reads from the UltraScale block RAM will not be granted when the Read Address Compare feature is active (RDADDRCHANGEA/B=1).

The intent of the Read Address Change feature is to save power by disabling a read access in cases where subsequent reads are made to the same address but the memory contents of that address have not changed. 

It is possible depending on block RAM use and placement that a read request will not be granted at the initial startup of the design after configuration when that feature is enabled. 

This only impacts block RAMs that are initialized to non-zero values and where a write is not issued on either block RAM port prior to the read access.

The Read Address Change feature can be activated in one of four ways:

  1. If it is manually set on the RAMB18E2 or RAMB36E2 instances by setting either RDADDRCHANGEA or RDADDRCHANGEB to 1
  2. If the Read Address Change option is enabled in Block Memory Generator
  3. If Vivado versions 2015.1 or 2015.2 were used with BRAM Power Optimization (default in opt_design).
  4. If Vivado versions 2015.4 or earlier is used and Power optimization (power_opt_design) is enabled in the design

Solution

For designs run in Vivado 2016.1 and later, a DRC is added to identify cases in which it is possible to see this read failure. 

The DRC will prevent a bitstream from being created before it is corrected. 

For designs run on earlier versions of Vivado, you can either run the DRC from 2016.1 on the checkpoint to identify whether a problem might exist, or the following Tcl command can be run in any Vivado version:

get_cells -hier -filter {PRIMITIVE_GROUP==BLOCKRAM && (RDADDRCHANGEA==TRUE || RDADDRCHANGEB==TRUE)}

If any block RAMs identified by this command are initialized, then it is possible this design can be impacted if those block RAM instances are read from prior to being written to. 

If it is uncertain whether this may impact the block RAM functionality, this feature can be disabled with the following Tcl commands in any Vivado version.

It can be run on a post-route checkpoint to avoid impacting timing or other place and route results:

set_property RDADDRCHANGEA FALSE [get_cells <BRAM_instance>]
set_property RDADDRCHANGEB FALSE [get_cells <BRAM_instance>]

The impact of disabling this feature is a possible increase in design power. The amount of power increase is dependent on how many RAMs have this feature enabled, how often the design does subsequent reads to the same address, and how fast the RAM is clocked.

However, it is expected that the total power increase should not be more than 1 or 2% in most cases.


Note: This issue only occurs in 20nm UltraScale designs and does not impact 16nm UltraScale+ designs.

Documentation will be updated to state that this feature is only allowed in un-initialized block RAMs for 20nm UltraScale designs.

AR# 66462
Date Created 01/22/2016
Last Updated 11/04/2016
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2015.3
  • Vivado Design Suite - 2015.4