When I implement a design, CPLDFit fails the fitting process with the following error message:
"Error: Design 'designname' has no outputs."
This may be caused by the following situations:
1. There is an incorrect connection in your design such that the outputs are not being driven. The fitter will remove all unconnected logic, thereby removing your outputs.
2. Ensure that you are setting the "Add I/O Buffers" option in your synthesis tool. The location of this option varies from vendor to vendor. For XST, this option is set to "On" by default, and is located in "Synthesize Properties", under the Xilinx Specific Options tab.