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AR# 66497

UltraScale FPGA Gen3 Integrated Block for PCI Express - Simulation in ModelSim/QuestaSim responds to all Cfg requests with UR

Description

When simulating a Gen3 core (PCIE_3_0) in either QuestaSim or ModelSim, UR completion status is received for all Type 0 Configuration requests.   


This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536) Xilinx Solution Center for PCI Express

Solution

Check the order of the library calls in the vsim command switches.

Incorrect:

-L simprims_ver -L unisims_ver -L unimacro_ver -L secureip

Correct:

-L unisims_ver -L unimacro_ver -L secureip -L simprims_ver 

 

Revision History:

04/27/2018 - Initial Release

AR# 66497
Date 04/27/2018
Status Active
Type General Article
IP More Less
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