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AR# 66505

UltraScale Component - I/O located in Bitslice [0] not available during delay calibration


When using Bitslice [0] of a nibble for a normal GPIO input mixed with Component or Native mode delays in the same nibble, the pin will not be active / available during calibration.

Once DLY_RDY is asserted, the pin will be active

Note: this Answer Record should not be viewed in isolation.

For all other known issues with component mode, please refer to (Xilinx Answer 66012).


Bitslice 0 is used for delay calibration. During the calibration, the I/O is not available, it only becomes available after DLY_RDY asserts.

This happens whenever a Delay that needs calibration is located in the nibble in either Component or Native mode. It does not matter whether the I/O at BITSLICE0 uses a delay or not.

The I/O pin is not available and might not have the desired value. A high input can be read as low.

At power-up, if the IDELAYCTRL does not have a clock, then the blockage could persist until the clock is supplied and the RDY finally asserts.

The DRC error for this condition was added in the 2016.1 release.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
66012 UltraScale - Known issues list when using component mode for I/O interfaces i.e IODELAY / IOSERDES. N/A N/A
AR# 66505
Date 01/24/2017
Status Active
Type General Article
  • Kintex UltraScale
  • Virtex UltraScale
  • Virtex UltraScale+
  • Kintex UltraScale+
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