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AR# 66505

UltraScale Component - I/O located in Bitslice [0] not available during delay calibration


When using Bitslice [0] of a nibble for a normal GPIO input with a mixture of Component or Native mode delays in the same nibble, the pin will not be active / available during calibration.

Once DLY_RDY is asserted, the pin will be active.

Note: this Answer Record should not be viewed in isolation.

For all other known issues with component mode, please refer to (Xilinx Answer 66012).


Bitslice 0 is used for delay calibration. During the calibration, the I/O is not available, it only becomes available after DLY_RDY asserts.

This happens whenever a Delay that needs calibration is located in the nibble in either Component or Native mode. It does not matter whether the I/O at BITSLICE0 uses a delay or not.

The I/O pin is not available and might not have the desired value. A high input can be read as low.

At power-up, if the IDELAYCTRL does not have a clock, then the blockage could persist until the clock is supplied and the RDY finally asserts.

The DRC error for this condition was added in the 2016.1 release.

DRC23-20 PDRC #1 Critical Warning The port <<name>> is assigned to a PACKAGE_PIN that uses BITSLICE_0 of a Byte that will be using calibration. The signal connected to <<name>> will not be available during calibration and will only be available after DLY_RDY asserts. If this condition is not acceptable for your design and board layout, <<name>> will have to be moved to another PACKAGE_PIN that is not undergoing calibration or be moved to a PACKAGE_PIN location that is not BITSLICE_0 or BITSLICE_6 on that same Byte. If this condition is acceptable for your design and board layout, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint: set_property UNAVAILABLE_DURING_CALIBRATION TRUE [get_ports exdes_rst_in]


There is one exception that is documented in (UG571): In an I/O bank, there is one differential QBC/GC pin set, or two single-ended QBC/GC pins. 

Those can be used to carry a clock to a BUFG, MMCM or PLL while BISC is running and while the possibly connected BITSLICE_0 is unavailable. 

The DRC will not flag for this exception.


Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
66012 UltraScale/UltraScale+ - Known issues list when using component mode for I/O interfaces i.e IODELAY / IOSERDES. N/A N/A
AR# 66505
Date 11/24/2017
Status Active
Type General Article
  • Kintex UltraScale
  • Virtex UltraScale
  • Virtex UltraScale+
  • Kintex UltraScale+
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