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AR# 66511

SelectIO - Vivado versions prior to 2016.1 are configured with a stronger drive than expected for HSTL_12, HSTL12_DCI, DIFF_HSUL_12_DCI and HSTUL_12_DCI

Description

Vivado versions prior to 2016.1 are configured with a stronger drive than expected for HSTL_12, DIFF_HSUL_12_DCI and HSUL_12_DCI

Solution

In Vivado versions prior to 2016.1, HSUL drivers default to an output impedance setting of RDRV_40_40.

In Version 2016.1 and beyond the settings will be RDRV_48_48.

For existing designs, the output impedance can be set to the RDRV_48_48 by opening a netlist design and selecting the pin planning view in the GUI.

Alternatively this can be set in the XDC file:

set_property OUTPUT_IMPEDANCE RDRV_48_48 [get_ports hstl12_out]

set_property OUTPUT_IMPEDANCE RDRV_48_48 [get_ports hsul12]

set_property OUTPUT_IMPEDANCE RDRV_48_48 [get_ports diff_hsul12_out]

AR# 66511
Date Created 01/29/2016
Last Updated 02/15/2016
Status Active
Type General Article
Devices
  • Zynq UltraScale+ MPSoC
  • Kintex UltraScale+
  • Virtex UltraScale+