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AR# 66528

Vivado 2015.4, Zynq-7000 AP SoC - PS DDRC ECC error counters do not increment during ECC errors

Description

When I use a Zynq-7000 PS DDR controller in ECC mode and an error occurs, the uncorrectable error counter and related ECC status registers are not updated.

These can include:


CHE_UNCORR_ECC_LOG_REG_OFFSET

CHE_UNCORR_ECC_ADDR_REG_OFFSET

CHE_ECC_STATS_REG_OFFSET.STAT_NUM_UNCORR_ERR


However, exceptions are still triggered to the CPU or other masters. How can I resolve this?

Solution

This issue is caused by the counters being held in a clear condition in the ps7_init function.

To work around the issue, release the clear register in the ps7_ddr_ecc_init() function of ps7_init.c:

       /*
         * Fix for CR#656095,
         */
        mask_write (PS7_DDR_CHE_ECC_CONTROL_REG_OFFSET, 0x00000003U, PS7_CLEAR_ERROR_ECC);
        mask_write (PS7_DDR_CHE_ECC_CONTROL_REG_OFFSET, 0x00000003U, 0);

A similar fix can be made in ps7_init.tcl for debugging sessions.

This issue is planned to be fixed starting in Vivado 2016.3.

AR# 66528
Date Created 02/02/2016
Last Updated 06/29/2016
Status Active
Type General Article
Devices
  • XA Zynq-7000
  • Zynq-7000
  • Zynq-7000Q
Tools
  • Vivado Design Suite - 2015.4.1
  • Vivado Design Suite - 2015.4
  • Vivado Design Suite - 2016.1
  • Vivado Design Suite - 2016.2
IP
  • Processing System 7