AR# 6655

FPGA Express - How do I do operator overloading in FPGA Express?

Description


General Description:

If I have two packages that have the same operator, how do I

chose which package the operator comes from? For example, the

Synopsys packages std_logic_signed and std_logic_unsiged both

have the "=" defined. If both packages are needed in the design,

which operator gets chosen?

Solution


To reolve this, the operator has to be declared as:



library.package_name."operator"



So in some VHDL code, the function would look like:



result <= IEEE.std_logic_unsigned."="(in1,"0000");
AR# 6655
Date 03/22/2011
Status Archive
Type General Article