UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 66565

LogiCORE DisplayPort v6.1 (Rev. 1) - Why is the lnk_fwdclk_p/n reference input clock grounded for the RX IP for UltraScale Devices?

Description

UltraScale devices require two clock sources for the DisplayPort RX IP. The first clock lnk_fwdclk_p is for the line rates 2.7 and 5.4, and this comes as a forwarded clock from the DP159 re-timer.

Because the forwarded clock frequency from DP159 for 1.62MHz line rate falls under the CPLL holes for the UltraScale devices, we need to provide a separate input clock of 270MHz.

 
Hence there are two reference clocks for the Display Port IP connected in the DP core as below
 
  • MGTREFCLK0 - lnk_clk_p/n - external fixed clock of 270MHz
  • MGTREFCLK1 - lnk_fwdclk_p/n - forwarded clock coming from the DP159
 

When I generate the DisplayPort RX core for any UltraScale Device and try to trace the lnk_fwd_clk connectivity to the MGTREFCLK1, it is connected to ground. 

What is the reason for this and how can I fix this?

Solution

This is a known issue in the Vivado 2015.4 DisplayPort v6.1 (Rev. 1) GUI.

This issue is resolved in Vivado 2016.1.

Please see (Xilinx Answer 66301) for a patch for the DisplayPort v6.1 (Rev. 1) in Vivado 2015.4.

 

Linked Answer Records

Master Answer Records

AR# 66565
Date Created 02/09/2016
Last Updated 04/01/2016
Status Active
Type General Article
Devices
  • Kintex UltraScale
  • Virtex UltraScale
Tools
  • Vivado Design Suite
IP
  • DisplayPort