UltraScale devices required two clock sources for the DisplayPort RX IP. The first clock lnk_fwdclk_p is for the line rates 2.7 and 5.4, and this comes as a forwarded clock from the DP159 re-timer.
Because the forwarded clock frequency from DP159 for 1.62MHz line rate falls under the CPLL holes for the UltraScale devices, we need to provide a separate input clock of 270MHz.
When I generate the DisplayPort RX core for any UltraScale Device and try to trace the lnk_fwd_clk connectivity to the MGTREFCLK1, it is connected to ground.
What is the reason for this and how can I fix this?
This is a known issue in the Vivado 2015.4 DisplayPort v6.1 (Rev. 1) GUI.
This issue is resolved in Vivado 2016.1.
Please see (Xilinx Answer 66301) for a patch for the DisplayPort v6.1 (Rev. 1) in Vivado 2015.4.