This article lists the current open PS DDR limitations with the configuration GUI in Vivado 2015.4.
1. As per the Zynq UltraScale+ Technical Reference Manual, 32-bit + ECC is supported:
On Page 271 it states:
"Error correction code (ECC) support in 32-bit and 64-bit mode, 2-bit error detection and 1-bit error correction."
However, in the IP GUI, it shows as Disabled without any drop-down option for 32-bit.
2. For DDR4 with an Effective DRAM Bus Width of 64-bit, the DRAM IC Bus Width can only go up to 32 bits.
3. 16-bit DDR support does not exist in the Zynq UltraScale+ controller and needs to be removed from the GUI.
These issues are planned to be fixed starting in Vivado 2016.1.