We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 66643

Zynq UltraScale+ MPSoC Processing System IP - AXI ACP Limitations


The ACP interface on Zynq UltraScale+ MPSoC accepts only the following (cache-line friendly) transactions. Masters targeting ACP should account for these limitations:

  • 64-byte aligned 64-byte read/write INCR transactions. All write-byte strobes must be the same (either enabled or disabled).
  • 16-byte aligned 16-byte read/write INCR transactions. Write-byte strobes can have any value.

All other transactions return an SLVERR response.


Transaction converter code is currently not planned to be provided by Xilinx. 

Consider using the coherent HPC ports instead of ACP which have broad AXI transaction support along with coherency.

AR# 66643
Date 04/21/2017
Status Active
Type General Article
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ MPSoC Processing System
Page Bookmarked