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AR# 66643

Zynq® UltraScale+™ MPSoC Processing System IP - AXI ACP Limitations

Description

The ACP interface on Zynq UltraScale+ MPSoC  accepts only the following (cache-line friendly) transactions. Masters targeting ACP should account for these limitations:
  • 64-byte aligned 64-byte read/write INCR transactions. All write-byte strobes must be same (either enabled or disabled).
  • 16-byte aligned 16-byte read/write INCR transactions. Write-byte strobes can have any value.
  • All other transactions return SLVERR response. 

Solution

Transaction converter code may be added to this Answer Record in the future. Contact Xilinx Technical Support for its availability.

AR# 66643
Date Created 02/17/2016
Last Updated 05/02/2016
Status Active
Type General Article
Devices
  • Zynq UltraScale+ MPSoC
IP
  • Zynq UltraScale+ MPSoC Processing System