I see the following error during Implementation. What is the reason for this error and how can I fix it?
This error complains about the sub optimal placement of I/O ports and BUFG in the design. This can be seen when the clock port is locked to a non-GCIO pin or when the I/O port and BUFG instance are placed in different clock regions.
If the clock port is locked to a GCIO pin and the error is still reported then follow the steps below:
1) Open the synthesized design and run the following commands:
This runs I/O and clock placement and leaves the partially placed design for investigation. "place_ports" might report an error but you can still view the partial placement.
2) Search for the instances mentioned in the error message and mark them in device view to find out in which clock region they are placed by the tool currently.
If the I/O and BUFG instances are placed in different clock regions then check if the BUFG is constrained to an improper site by user location constraints.
Check the IS_FIXED property of the BUFG instance to find this out. If the IS_FIXED property is set it means that it is locked by user constraints. If this is the case, modify the constraints so that the I/O port and BUFG get placed in same clock region.
3) Try locking the BUFG to the same clock region as that of I/O port using the following constraint:
set_property CLOCK_REGION XxYy [get_cells <bufg_instance_name>]
You can also override the error by using the CLOCK_DEDICATED_ROUTE constraint mentioned in the error message, however this is not recommended.