AR# 66668

Vivado - Successfully packing a register into an IOB with Vivado


This article describes what is necessary to successfully pack a register into an IOB using Vivado. The IOB can be specified as either an RTL attribute or through an XDC constraints file. 

Through both methods, the IOB property will be set as a property on either a port or cell (register).


Properly packing a input/output register into an IOB depends on the eligibility of the logical connection and the availability of the IOB.

Eligibility - A register can only be packed into an IOB if it is eligible during place_design. If not, the register will be placed in the fabric.

  • Ineligible Output FF Driving both port & LUT - Warning - To ensure a register can be successfully be packed into an IOB, make sure that there is only one logical connection between the top-level port and the FF to be packed into the IOB.
    In the below example, the coding style has an output register driving a top-level port, but also driving combinational logic. The connection to the combinational logic requires routing to the fabric LUT.
    This connection is not available from the output of an IOB register which makes this FF ineligible for IOB packing. The below messaging should be seen with this type of connection:

[Shape Builder 18-132] Instance dout_reg has IOB = TRUE property, but it cannot be placed in an OLOGIC site. Instance dout_reg cannot be placed in site OLOGIC_X1Y0 because the output signal of the cell requires general routing to fabric and cells placed in OLOGIC can only be routed to delay or I/O site.


How to apply the IOB attribute/constraint. - Although the IOB constraint can be placed on both a top-level port or cell (register), it is advised to apply it specifically to a register connected to a port.

  • Specifying IOB on port - Warning - In the below schematic, a single top-level port has an IOB constraint specified, but is connected to at least two registers.
    One register can still be packed into an IOB, leaving the other to be placed into a fabric SLICE site.

[Constraints 18-841] Port din_b has IOB constraint. But it drives multiple flops. Please specify IOB constraint on individual flop. The IOB constraint on port will be ignored.


  • Specifying IOB on port - Error - In the below schematic, an error is produced when two output registers with an IOB property are connected to an IOBUF. The IOB has been set on the top-level port I/O, but is propagated to both registers.
    In this case, to avoid the error the IOB should be set on one of the individual registers.

[DRC 23-20] Rule violation (AVAL-248) OBUFT_has_two_FFs_with_IOB - The OBUFT IOBUF_inst has I (data) pin driven by Flop FDRE_I and T (tri-state) pin driven by Flop FDRE_T, both of which have the IOB attribute set. This cannot be honored by placement in this device architecture, which has only one register available in the IOB.


Architecture specific Guidance - Architectural differences can pose challenges when migrating a design, and require specific changes.

  • UltraScale 3-state registers - 3-state SDR registers will need to be implemented in fabric logic instead of an IOB. For more information, see (Xilinx Answer 62490).

Effect of other attributes/constraints on IOB - Applying other attributes/constraints on the same port or cell as an IOB can affect the packing of a register with the IOB attribute

  • DONT_TOUCH/KEEP constraints - Using a DONT_TOUCH/KEEP/MARK_DEBUG type of RTL attribute or XDC constraint can prohibit or enable an IOB packing depending on the need of the design. (Xilinx Answer 62099) details how a DONT_TOUCH can prevent necessary synthesis optimization.
    A DONT_TOUCH/KEEP constraint can also help an IOB packing if synthesis optimization prevents an IOB from being packed. A design should be checked at the elaborated and post-opt_design stages to determine if there has been any change in eligibility for a register which is intended to be packed into an IOB.

Difference from ISE

  • Unlike ISE, there is no value for "FORCE". In Vivado, IOB=TRUE is a hard constraint that cannot be disregarded as in ISE.

How to Verify an IOB Packing - There are a few ways to verify the success of an IOB packing. These are described in (Xilinx Answer 62661).

AR# 66668
Date 03/25/2016
Status Active
Type General Article