Description

This example design sets up the TRACE port (routed via EMIO to the MICTOR connector on the board).

Solution

The IP Integrator diagram will look like the following screen capture:

• The LED is just an easy way to see if the clock is running (optional).
• This design does not include any re-timing on the TRACE interface. It assumes that the third party debugger (For example, Lauterbach) is capable of doing the re-timing if required.

The XDC constraints for the TRACE signals are attached.

You can export the hardware to SDK and build a simple BOOT.bin (FSBL + bitstream + hello_world).

Note 2:

IMPORTANT: Please see (Xilinx Answer 66436) XSDB is not able to connect to PSU after successfully booting in SD mode on ZCU102.

Once it has booted (for example from the SD card), the TRACE port is available on the MICTOR connector on the board for the third party debugger to use.

Note 3: 

• Ensure that J88 has a jumper on it to provide the 3.3V reference voltage to the debugger TRACE port.
• The MICTOR only connects the TRACE signals (clk, ctl, data[15:0]). it does not connect the JTAG signals (tdi, tdo, tck, tms).

Note 4

Zynq UltraScale+ MPSoC and Zynq-7000 do not use the following TRACE signals:

• TRACEDBGRQ
• TRACEDBGACK
• TRACEEXTTRIG
• TRACETRST_B
• TRACESRST_B

These signals can be left unconnected on the MICTOR or inside the PL.

Attachments

Associated Attachments