Version Found: N/A
For designs with two separate High Speed SelectIO Wizard interfaces within a bank, the reset sequence will not complete until both interfaces have been reset. The reset state machine will stop in the state waiting for DLY_RDY from the BITSLICE_CONTROL when only one of the interfaces has been reset.
Note: this Answer Record should not be viewed in isolation.
For all other known issues and to see what version of Vivado / High Speed SelectIO Wizard these issues have been resolved in, please refer to (Xilinx Answer 64216)
For a given bank, all 8 of the BITSLICE_CONTROLs are cascaded together even though an interface may only span one or more byte groups.
In a case where two separate interfaces are being used within a bank, this might result in some of the BITSLICE_CONTROL blocks being held in reset, which affects the DLY_RDY of the interface being reset.
The solution is to apply the reset at the same time. This will start the reset sequence, and the DLY_RDY signals for all of the BITSLICE_CONTROLs will be released.
Each interface can then separately proceed through the reset of the reset sequence.