Version Found: v7.1 Memory IP
Version Resolved: See (Xilinx Answer 58435)
Vivado and the UltraScale Memory IP use an absolute path to point to the custom imported CSV file.
This causes problems if the project is moved from its original location.
To resolve this problem, the Memory IP should only be moved using the "Project Archive" option in Vivado. The output products and synthesized DCP should then be regenerated.
If "Project Archive" cannot be used, then the IP must be regenerated from scratch, or the following steps can be followed:
Option 1:
Option 2 :
Use the following Tcl commands after synthesis on the synthesized DCP:
set_property CustomPartAbsPath [file normalize ../../<relative path to CSV file>.csv] [get_cells -hierarchical -filter {REF_NAME == <MIG top-level name>}]
write_checkpoint -force [lindex [find_top] 0].dcp
For future designs, starting in Vivado 2016.1, the "Project Archive" option should be used.
Older IP brought into Vivado 2016.1 should be upgraded as the CSV file path is also removed from the DCP to resolve any opt_design errors.
Revision History:
Initial Release - 02/22/2016
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
58435 | MIG UltraScale - IP Release Notes and Known Issues for Vivado 2014.1 and newer tool versions | N/A | N/A |