Version Found: v1.1
Version Resolved: See (Xilinx Answer 69037)
After the production release of the UltraScale RLDRAM3 v1.1 IP (available with Vivado 2015.4) there was an enhancement to the system reset structure.
This is included into the IP starting in the 2016.1 releases and later versions. For customers currently in production that are unable to upgrade to Vivado 2016.1, Xilinx recommends installing the provided patch update to take advantage of the IP improvements.
This patch contains an update to the reset structure to synchronously assert and deassert the MMCM, Fabric, RIU and MicroBlaze modules for the entire memory subsystem. For more information, please refer to (PG150).
To install the patch, extract the contents of "AR66689_Vivado_2015_4_preliminary_rev1.zip" to the 2015.4 install directory (for example, C:\Xilinx\Vivado\2015.4\), then open Vivado 2015.4 and generate or regenerate all of the RLDRAM3 IP.
Note: This tactical patch is only compatible with the Vivado 2015.4 and RLDRAM v1.1 IP.
04/16/2016 - Initial Release
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