After instantiating the STARTBUF cell in your HDL source, FPGA Express does not recognize
this component and gives this message:
Warning: Cannot link cell 'use_gsr/U2' to its reference design 'STARTBUF'. (FE-LINK-2)
Warning: The cell '/use_gsr/U2' is not linked to any design. (FE-CHECK-4)
Use of the STARTUP module is not listed in the reports.
The STARTBUF module is not listed in the FPGA Express synthesis library, so it cannot be
recognized by the software. However, the Xilinx tools do know this module, so the STARTBUF
is correctly mapped into the STARTUP block. Therefore this warning can be safely ignored
(this can be verified by looking at the implementation reports in Foundation).
A second option is to simply instantiate the STARTUP block instead of the STARTBUF.
An example of this can be found in the Language Assistant.