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AR# 66715

2016.1 Zynq UltraScale+ MPSoC - QSPI programming on a Zynq UltraScale+ device requires boot in JTAG mode

Description

We are programming QSPI flash with a custom board which requires the Zynq UltraScale+ device to boot in JTAG mode from both XSDK and Vivado Hardware Manager.

QSPI programming on a ZCU102 board requires the Zynq UltraScale+ device to boot in JTAG mode from both XSDK and Vivado Hardware Manager.

Note: this Answer record applies to the 2016.4 release as well as earlier versions. Please see below for differences.

Solution

The programming flow is to set the boot mode pins to JTAG and issue a PS_POR_B before programming the QSPI.

The programming flow also requires you to specify an FSBL that runs on A53 (an FSBL running on R5 will not work) to help the programmer to initialize the system.

If you are QSPI programming with SDK 2016.3 and older, the FSBL should be generated for an A53 processor only.

 


 

 

 

For the 2016.4 SDK and later versions, FSBL can run from either an A53 or R5 processor while QSPI indirect programming:

 

ar_r5_fsbl.JPG



 

Note: This is not a silicon requirement, it is a tool limitation. This applies to the 2016.4 release as well. 

Future Vivado releases will not have this limitation and it will be possible to program QSPI in Production Silicon when booting in QSPI boot mode.

 

AR# 66715
Date 04/11/2017
Status Active
Type General Article
Devices
  • Zynq UltraScale+ MPSoC
Tools
  • Vivado Design Suite - 2015.4.2
  • Vivado Design Suite - 2015.4.1
  • Vivado Design Suite - 2015.4
  • More
  • Vivado Design Suite - 2016.1
  • Vivado Design Suite - 2016.2
  • Vivado Design Suite - 2016.3
  • Vivado Design Suite - 2016.4
  • Less
Boards & Kits
  • Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit