(UG885), VC707 Evaluation Board User Guide (v1.6.1) Table 1-26 lists the GPIO Pin Connections to FPGA U1.
The CPU_RESET net name connection does not match the VC707 schematic (rev 1.0).
What is the correct connection?
GPIO Connections to FPGA U1 are listed in Table 1-26 on Page 54 of (UG885) v 1.6.1.
For Pin "AV40", schematic net name "CPU_RESET", the GPIO Pin connection is listed as SW3.3 in Table 1-26, which is incorrect.
The correct connection, as confirmed by the VC707 Schematic (Rev 1.0), is CPU_RESET connected to Push Button SW8.
The correct connection is SW8.3.
(UG885) will be updated to reflect this.
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