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AR# 66780

Vivado 2016.3, AXI SmartConnect - Release Notes and Known Issues


The Xilinx LogiCORE IP AXI SmartConnect core connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices.

The AXI SmartConnect IP core is currently pre-production and is not license controlled. The IP is suitable for evaluation, but is not yet recommended for production designs.


2016.3 Pre-Production Limitations

  • The SmartConnect IP is only available in Vivado IP Integrator
  • In Vivado IP Integrator, Designers Assistance connection automation can connect IP blocks to an existing SmartConnect when there are no AXI Interconnect v2.1 IPs in the block diagram. Designers assistance cannot instantiate a new SmartConnect and will make connections to existing AXI Interconnect v2.1 IPs if both exist.
  • There are no transaction acceptance limits enforced at this time. Transactions received on the SI are issued to the MI up to the point at which internal command queues become filled, at which time further commands are stalled until buffer space becomes available.
  • Exclusive access transactions (using the AXI ARLOCK/AWLOCK signal) are not supported at this time. Any transaction received with ARLOCK/AWLOCK asserted will be propagated to the MI with ARLOCK/AWLOCK de-asserted.
  • Clock-enable (aclken) inputs are not supported at this time.
  • No area-optimized mode is supported by SmartConnect at this time. Continue to use axi_interconnect_v2_1 in area strategy mode for minimal area applications and for all pure AXI4-Lite solutions.
  • SmartConnect does not preserve ID bits and transaction characteristics necessary for Exclusive Accesses
  • Only round-robin arbitration is supported
  • Endpoint MI multi-threading is not supported. Endpoint AXI slaves connected to SmartConnect will receive a fixed ID
  • SmartConnect utilizes AXI Meta data in IP Integrator in order to optimize itself. Area, latency, and timing can be improved if the AXI master emits AXI meta data to indicate:
    • The IP uses only INCR burst (HAS_BURST=0)
    • The IP does not require sub-size burst support (SUPPORTS_NARROW=0)
    • The IP is read-only or write-only (READ_WRITE_MODE)
    • The max burst length of the IP is known (MAX_BURST_LENGTH)

2016.1/2016.2 Beta Users

  • Users of the Beta version of SmartConnect released in Vivado 2016.1 and Vivado 2016.2 should immediately move to the 2016.3 release of SmartConnect. The Beta versions are no longer supported and are not backward compatible with the 2016.3 version.


AR# 66780
Date 10/13/2016
Status Active
Type Release Notes
  • Vivado Design Suite - 2016.1
  • Vivado Design Suite - 2016.2
  • Vivado Design Suite - 2016.3
  • AXI SmartConnect