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AR# 66780

AXI SmartConnect - Release Notes and Known Issues

Description

The Xilinx AXI SmartConnect LogiCORE IP core connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices.

Solution

2017.1& Limitations/Known Issues

  • The SmartConnect IP is only available in Vivado IP Integrator
  • There are no transaction acceptance limits enforced at this time. Transactions received on the SI are issued to the MI up to the point at which internal command queues become filled, at which time further commands are stalled until buffer space becomes available.
  • Exclusive access transactions (using the AXI ARLOCK/AWLOCK signal) are not supported at this time. Any transaction received with ARLOCK/AWLOCK asserted will be propagated to the MI with ARLOCK/AWLOCK de-asserted.
  • Clock-enable (aclken) inputs are not supported at this time.
  • No area-optimized mode is supported by SmartConnect at this time. Continue to use axi_interconnect_v2_1 in area strategy mode for minimal area applications and for all pure AXI4-Lite solutions.
  • SmartConnect does not preserve ID bits and transaction characteristics necessary for Exclusive Accesses
  • Only round-robin arbitration is supported
  • Endpoint MI multi-threading is not supported. Endpoint AXI slaves connected to SmartConnect will receive a fixed ID
  • It is not recommended to use SmartConnect in a 1x1 configuration to perform in-line AXI conversion or buffering functions, such as data-width conversion or protocol conversion. Continue to use the appropriate V2.1 AXI coupler IP for such in-line conversions.
  • While multiple instances of SmartConnect can be cascaded, it is not recommended to connect SmartConnect to AXI Interconnect V2.x, or vice-versa. The only V2.1 AXI coupler IP that is approved to connect to SmartConnect is AXI Register Slice V2.1.
  • SmartConnect uses AXI Meta data in IP Integrator in order to optimize itself. Area, latency, and timing can be improved if the AXI master emits meta data on its AXI interface to indicate. For custom logic, this is accomplished during IP packaging:
    • The IP uses only INCR burst (HAS_BURST=0)
    • The IP does not require sub-size burst support (SUPPORTS_NARROW=0)
    • The IP is read-only or write-only (READ_WRITE_MODE)
    • The max burst length of the IP is known (MAX_BURST_LENGTH)

2016.1/2016.2 Beta and 2016.3/2016.4 Preproduction Users

  • Users must move to the 2017.1 and later release of SmartConnect. The Beta/Pre-production versions are no longer supported and are not backward compatible.

 

AR# 66780
Date 04/19/2017
Status Active
Type Release Notes
Tools
  • Vivado Design Suite - 2016.1
  • Vivado Design Suite - 2016.2
  • Vivado Design Suite - 2016.3
IP
  • AXI SmartConnect