The Xilinx LogiCORE IP AXI SmartConnect core connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices.
The AXI SmartConnect IP core is currently pre-production and is not license controlled. The IP is suitable for evaluation, but is not yet recommended for production designs.
2016.3 Pre-Production Limitations
2016.1/2016.2 Beta Users