AR# 66788


Design Advisory for MIG 7 Series DDR3 - DQS_BIAS is not properly enabled for HR banks causing potential calibration failures


This Design Advisory is being released as a notification of calibration failures that have been seen within MIG 7 Series DDR3 designs meeting ALL of the following criteria:

  • Memory interface in a High Range (HR) I/O bank
  • Memory interface frequency of 400Mhz and higher
  • Memory interface IP version 2.3 or later
  • Vivado version prior to 2016.1

MIG 7 series DDR3 designs NOT meeting all of the above criteria are unaffected by this Design Advisory.

A device model issue has been found for DDR3 HR bank designs starting with MIG v2.3 released with Vivado 2014.4. 

The model issue results in internal I/O termination not being enabled on DQS differential I/O pairs. This can result in the DQS preamble being improperly detected during DQSFOUND calibration, resulting in calibration failures during OCLKDELAYED and MPR Read Leveling calibration phases.

This incorrect preamble detection can only occur during calibration. Therefore, if a design passes calibration, the problem will not appear later during operation.


Xilinx recommends that all affected customers apply the fix. Not applying the patch might lead to intermittent calibration failures.

For products already deployed in the field, the update is recommended but not required. For production designs with new shipments and all new designs, the update is recommended.


This Design Advisory includes a Vivado patch that updates the DQS HR I/O model.

The AR66788_vivado_201x_x_preliminary_rev2.txt file delivered with the patch includes the steps for patch installation. This issue is fixed in Vivado 2016.1 and a patch will no longer be required.

Please note, after applying the software patch, only Generate Bitstream needs to be re-run. The design does not need to be re-synthesized or re-implemented.

Note: An earlier patch,, is only applicable for bitstream generation, hence it must be replaced with provided below so that the patch can be used through the entire design process (Synthesis, Link, Optimize, Place, Route and Generate Bitstream).

An earlier patch,, must be replaced with provided below.

Revision History:

03/23/2016 Initial Release
04/13/2016 Updated frequency information and uploaded rev2 patches
06/06/2016 Updated limitation info using rev1 patch


Associated Attachments

Linked Answer Records

Master Answer Records

AR# 66788
Date 05/03/2016
Status Active
Type Design Advisory
People Also Viewed