We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 66794

UltraScale DDR3 IP - Write errors may be seen in dual rank or dual slot configurations in Vivado 2015.3 or 2015.4 due to Dynamic ODT settings


Version Found: UltraScale DDR3 v1.0

Version Resolved: See (Xilinx Answer 58435)

UltraScale DDR3 dual rank or dual slot IP designs might exhibit write data errors in the v1.0 (Vivado 2015.3) and v1.1 (Vivado 2015.4) releases.

These write errors are due to a change in the ODT settings within the IP. Modification to one ODT setting for these two IP releases is required and documented below.


The ODTWR parameter must be updated for the below configurations.

This parameter is set within the "rtl/ip_top/core_name_ddr3.sv" module and needs to be updated as shown below.

To modify IP RTL, please follow the "Editing IP Sources" section of (UG896)

DDR3 IP Configuration IP Generated ODTWR Setting Updated/Correct ODTWR Setting
Dual Slot, 2 Single Rank DIMMs 0x0012 0x033
Single Slot, 1 Dual Rank DIMM 0x0012 0x033
2 Dual Rank DIMMs 0x7BDE 0xFFFF

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58435 DDR4, DDR3, QDRIV, QDRII+, RLDRAM3, LPDDR3 UltraScale and UltraScale+ - IP Release Notes and Known Issues N/A N/A
AR# 66794
Date 04/06/2016
Status Active
Type Known Issues
  • Kintex UltraScale
  • Virtex UltraScale
  • MIG UltraScale
Page Bookmarked