AR# 66800

UltraScale Memory IP - When the reset_n pin is located in a bank with an I/O Standard that has an incompatible voltage level, the following error is seen during 'opt_design': [Mig 66-99]

Description

Version Found: Vivado 2016.1

Version Resolved: See (Xilinx Answer 58435)

The JEDEC standards and data sheets for all memory types require that the reset_n pin be driven at the appropriate voltage level. For DDR4 the compatible IOSTANDARD is LVCMOS12 and for DDR3 it is LVCMOS15.

However, it is common for the reset_n to be located in a bank that does not meet this requirement.

If this situation exists then the following error message will be seen during 'opt_design':

[Mig 66-99] Memory Core Error - The memory reset port <reset_n> has an incompatible IO Standard <IO Standard> selected. If a level shifter or similar is used to ensure compatibility, this DRC can be demoted. Apply 'set_param memory.dontrundrc true' post after synthesis and apply 'set_property is_enabled false [get_drc_checks MIG-69]' post opt_design to bypass this DRC and proceed to bitstream generation. For more details please see (Xilinx Answer 66800).

Solution

If a level shifter or similar circuitry is used to ensure compatibility, then the following steps can be taken to bypass the error message:


Steps for Project Based Mode and using the Vivado GUI:

  1. Create a Tcl file and add the following commands:
    set_param memory.dontrundrc true
    set_property is_enabled false [get_drc_checks MIG-69]
    Note: The first command disables all Memory DRC checks during 'opt_design' only and the second disables only the specific incompatible I/O standard DRC during implementation
  2. In Vivado, select Implementation Settings > tcl.pre and point to your saved Tcl file from Step 1.
  3. Create a second Tcl file and add the following command:
    set_property is_enabled false [get_drc_checks MIG-69]
  4. In Vivado, select Bitstream Settings > tcl.pre and point to your saved Tcl file from Step 3
  5. Run through Synthesis, Implementation, and Generate Bitstream
    Note: If steps 3-5 are not followed the following DRC error message will be seen:


ERROR: [DRC 23-20] Rule violation (MIG-69) Invalid Constraint - [<instance>] The Memory IP reset port reset_n has an incompatible IO Standard <IO Standard> selected. If a level shifter or similar is used to ensure compatibility, this DRC can be demoted. For more details please refer AR66800.


Steps for Non-Project Based Mode, Batch Mode, or Tcl Mode:

  1. Apply "set_param memory.dontrundrc true" in the Tcl console prior to running 'opt_design'.
    Note: This will disable all Memory DRC checks during 'opt_design' only.
  2. After 'opt_design' has completed, apply "set_property is_enabled false [get_drc_checks MIG-69]" in the Tcl console prior to running 'place_design'.
    Note: This will disable only the DRC check for the reset_n voltage level and all other Memory DRC checks will not be enabled.

    If step 2 is not followed the following DRC error message will be seen:


ERROR: [DRC 23-20] Rule violation (MIG-69) Invalid Constraint - [<instance>] The Memory IP reset port reset_n has an incompatible IO Standard <IO Standard> selected. If a level shifter or similar is used to ensure compatibility, this DRC can be demoted. For more details please refer AR66800.

Revision History:

03/24/2016 - Initial Release

09/18/2017 - Linked to master AR58435

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58435 MIG UltraScale - IP Release Notes and Known Issues for Vivado 2014.1 and newer tool versions N/A N/A
AR# 66800
Date 01/19/2018
Status Active
Type General Article
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IP