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AR# 66822

AXI 10G Ethernet Subsystem "Frame Errors in example design" Hardware and Simulation


The following Error can occur in Vivado 2015.4.

The example design indicates a frame error in hardware and in simulation. The error is immediately visible in hardware, either by the indicator LEDs if you load it onto a KC705, or ILAs triggering on "frame_error". The error shows up in simulation after approximately 150uS of simulation time.

The error is created by a bug in the traffic generator and pattern checker's TX FIFO. The pattern checker does not respond correctly to back pressure from the TX FIFO and causes the expected packet size value to incorrectly increase.

The frame checker checks the received packet's size against the expected packet size to see if the packet was sent and received correctly. Once the expected packet size value gets out of sync with the actual packet size value, frame_error asserts and never corrects itself.


This incorrect behavior is fixed in Vivado 2016.1.

If you run into this error in Vivado 2015.4, you can copy in the following files from the 2016.1 example design to fix the issue:






AR# 66822
Date 04/07/2016
Status Active
Type General Article
  • AXI 10 Gigabit Ethernet
Boards & Kits
  • Kintex-7 Boards and Kits
  • Virtex-7 Boards and Kits