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AR# 66826

JESD204 - Reset pulse width information


For a JESD204 core, what is the rx_reset_gt reset pulse width set to?


For JESD204, the reset pulse for the rx_reset_gt signal is held high for 12 AXI clock cycles. This is to ensure that the reset pulse is seen if the AXI clock is much faster than the DRP clk.

The pulse is held high for 12 AXI clock cycles as the rx_reset_gt output from the JESD204 core is in the AXI clock domain and not the core clock domain.

From Vivado 2015.3 onwards only the GT channels are reset and not the PLLs.

AR# 66826
Date 03/25/2016
Status Active
Type General Article
  • JESD204