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AR# 66843

Vivado Simulator - How to read files in VHDL/Verilog using relative paths without adding them to the project?


Vivado Simulator returns an error for files referenced using relative paths:

Vivado Simulator 2015.4
ERROR: File ../Text/1.txt could not be opened
on HDL file /group/xhdwts/yash/10346701/Deb/project_2/project_2.srcs/sources_1/new/Testbench.vhd line 29
ERROR: [Simtcl 6-50] Simulation engine failed to start: The Simulation shut down unexpectedly during initialization.
Please see the Tcl Console or the Messages for details.


For Vivado Simulator the relative paths in the VHDL/Verilog file are with reference to the file which is being parsed, not the project environment.

For example:

The relative path I use in the Testbench.vhd file refers to the Testbench.vhd file location.

If the Testbench.vhd file location is "W:\yash\10346701\Deb\project_2\project_2.srcs\sources_1\new" and the 1.txt file location is "W:\yash\10346701\Deb\Text" I will use the relative path "../../../../Text/1.txt" 

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
56961 Vivado Simulator: How to read files in VHDL or Verilog code using Relative Paths? N/A N/A
AR# 66843
Date 04/15/2016
Status Active
Type General Article
  • FPGA Device Families
  • Vivado Design Suite
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