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AR# 66860

2015.3 – Vivado Logic Debug – [Labtools 27-1972] Mismatch between the design programmed into the device XXXX (JTAG device index = X) and the probes file path/impl_6/debug_nets.ltx.


I am seeing the following error after programming my device:

ERROR: [Labtools 27-1972] Mismatch between the design programmed into the device xc7k325t (JTAG device index = 0) and the probes file <path>/impl_6/debug_nets.ltx.

The core at location user chain=1 index=0 has different widths for ILA input port X. Port width in the device core is X, but port width in the probes file is X.


  1. Reprogram device with the correct programming file and associated probes file
  2. Go to the device properties and associate the correct probes file with the programming file already programmed in the device.


This error is seen when there is a mismatch between a .bit file and .ltx file.

Sometimes changes made in the ILA are not reflected in the .ltx file, causing a mismatch between the .ltx and .bit file.

To work around the issue, please do the following:

  1. Open the synthesized design.
  2. Use the following Tcl command:
write_debug_probes -force filename.ltx

Use the new .ltx file when programing the board.

AR# 66860
Date 04/18/2016
Status Active
Type General Article
  • Artix-7
  • Kintex UltraScale
  • Kintex UltraScale+
  • Kintex-7
  • Vivado Design Suite
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