In 7 Series FPGAs with multi-function HR I/O in banks 14/15 or in Zynq-7000 AP SoCs with HR I/O in banks 34/35, the HR I/O in those banks might have a 0-1-0 transition during power-on for the affected implementation shown below.
Affected Implementation - All of the following must be true for the potential I/O transition to occur:
When the affected implementation is present, the I/O in the 7 series FPGA banks 14/15 or Zynq-7000 AP SoC banks 34/35 can have 0-1-0 when the applicable bank VCCO ramps through the ~2.1V voltage level.
The duration of the 1 depends on the VCCO ramp rate and has been observed to range from a few microseconds up to 2 milliseconds, depending on the VCCO ramp rate. Slower VCCO ramp rates can result in longer duration of the 1.
To avoid the 0-1-0 transition in affected HR I/O banks, use one of the following solutions: