AR# 66901

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JESD204 - Reset settings

Description

Is there a request sequence when using the JESD204 IP and the JESD204 PHY IP?

Are there reset settings that need to be observed when using JESD204 IP and JESD204 PHY IP?

Solution

Reset Connections:

  • Tx_reset and rx_reset, tx_sys_rst and rx_sys_rst should all be connected
  • Tx_sys_rst and rx_sys_rst should be connected to the reset source that drives the tx_reset and rx_reset input to the JESD204 core
  • Tx_reset_gt of the JESD204 Tx should be connected to tx_reset_gt of the JESD PHY
  • Rx_reset_gt of the JESD204 Rx should be connected to rx_reset_gt of the JESD PHY

Resets need to be connected as above. The sys_resets perform a complete reset of the transceiver (channel and PLL), whereas the gt_reset only resets the channel, leaving the PLL running.

This reset is connected to the JESD204 reset output.

Once the sys_resets are deasserted, the GTs have an internal state machine which resets the GT and signal DONE once this process is complete.


Reset Signal Timing Requirements

Reset signals are asynchronous resets that get synchronized into the DSP clock domain in the PHYs block level.

There are no specific timing requirements on the reset signals, but any JESD design should meet timing in the Vivado tools.


Reset Pulse

For the JESD204 core, the reset pulse for the rx_reset_gt signal is held high for 12 AXI clock cycles.

This is to ensure that the reset pulse is seen if the AXI clock is much faster than the DRP clk.

The pulse is held high for 12 AXI clock cycles as the rx_reset_gt output from the JESD204 core is in the AXI clock domain and not the core clock domain.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
69884 JESD204 Solution Center - Design Assistant - Resets N/A N/A
66354 JESD204 Solution Center - Design Assistant - General Debug Tips N/A N/A
AR# 66901
Date 03/28/2019
Status Active
Type General Article
IP
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