Is there a request sequence when using the JESD204 IP and the JESD204 PHY IP?
Are there reset settings that need to be observed when using JESD204 IP and JESD204 PHY IP?
Resets need to be connected as above. The sys_resets perform a complete reset of the transceiver (channel and PLL), whereas the gt_reset only resets the channel, leaving the PLL running.
This reset is connected to the JESD204 reset output.
Once the sys_resets are deasserted, the GTs have an internal state machine which resets the GT and signal DONE once this process is complete.
Reset Signal Timing Requirements
Reset signals are asynchronous resets that get synchronized into the DSP clock domain in the PHYs block level.
There are no specific timing requirements on the reset signals, but any JESD design should meet timing in the Vivado tools.
For the JESD204 core, the reset pulse for the rx_reset_gt signal is held high for 12 AXI clock cycles.
This is to ensure that the reset pulse is seen if the AXI clock is much faster than the DRP clk.
The pulse is held high for 12 AXI clock cycles as the rx_reset_gt output from the JESD204 core is in the AXI clock domain and not the core clock domain.