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AR# 66920

Vivado Synthesis - Port defined as a record that contains a null vector gets entire record/port ignored


When synthesizing VHDL that has an entity with a port defined as a record, and one of the elements of the record is a vector of size 0, the whole port is ignored during Synthesis.

The following warning message is given:

Warning:[Synth 8-506] null port 'tRecordIn' ignored ["Top.vhd":71]

Is this incorrect behavior?


This is expected behavior with the current implementation for handling null ports.

If an element of a record is null then the whole record is considered null.

It is recommended to avoid using a null vector in the record.

AR# 66920
Date 04/05/2016
Status Active
Type Known Issues
  • Vivado Design Suite
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