AR# 66927

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UltraScale DDR4/DDR3 - BFM simulations have errors when using Self Refresh and Self Restore options

Description

Version Found: DDR4 v2.0, DDR3 v1.2

 

Version Resolved: See (Xilinx Answer 69035) for DDR4 and (Xilinx Answer 69036) for DDR3.

When running a DDR4 IP behavioral simulation with Self Refresh and Self Restore enabled the following error message might be seen:

sim_tb_top.mem_model_x16.mem.memModels_Ri2[0].memModel2[0].ddr4_model.always_diff_ck
.if_diff_ck.sref_decode:ERROR: Initialization sequence must be complete prior to cmdSREFE @1937345

When running a DDR3 IP behavioral simulation with Self Refresh and Self Restore enabled the following error message might be seen:

sim_tb_top.mem_model_x4.memRank[3].memModel[17].u_ddr3_x4.reset: at time 0.0 ps ERROR: CKE must be inactive when RST_N goes inactive.

Solution

These issues only occurs when using the BFM model for simulations and can be safely ignored.

Revision History:

  • 10/05/2016 - Updated for DDR3
  • 04/16/2016 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
69036 UltraScale/UltraScale+ DDR3 - Release Notes and Known Issues N/A N/A
69035 UltraScale/UltraScale+ DDR4 - Release Notes and Known Issues N/A N/A
AR# 66927
Date 01/02/2018
Status Active
Type General Article
Devices
Tools
IP
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