Does Xilinx offer a way to pre-compile IP files for simulation in order to speed up on compilation time? Currently I do not see a way to do this in the GUI or via a Tcl command.
Starting in Vivado 2016.1, IP files are compiled with UNISIM and SIMPRIM libraries as part of running compile_simlib (Tcl mode).
In Vivado 2016.1, an Early Access feature exists to have Vivado generated simulation scripts leverage the compiled IP libraries.
Please contact Xilinx Tech Support to learn more about this capability.
Starting in the 2016.3 release, compile_simlib (Tcl mode and IDE) will compile static simulation files for IP by default.
Pre-Compiled IP simulation libraries are now used by default in Vivado 2016.3.