We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 66941

Vivado 2015_3 DXAUI core Example design fails in Simulation.


The DXAUI core Example design fails in Simulation.


This is a known issue found in Vivado 2015.3. It occurs because an incorrect reference clock frequency (78.125Mhz) is propagated to the GT subcore instead of the frequency selected in the GUI. This issue is fixed in Vivado 2015.4.

As a work-around you can follow the below procedure to change the GT reference clock to the correct reference clock frequency (the one selected in the GUI during core generation).

The following example is for a reference clock selection of 156.25Mhz.

1) Create a separate project with the same settings as your project in a separate directory (this will avoid a file name clash).

2) Click "Add Sources" and "Add Existing IP"


3) Add xaui_0_gt.xci which will be present in a similar hierarchy to the following:


4) Recustomize the GT XCI and change the reference clock to 156.25Mhz from 78.125Mhz as shown below.


5) Generate the core.

6) Replace the files present in /Dxaui_Ex\xaui_0_example\xaui_0_example.srcs\sources_1\ip\xaui_0\ip_0 with the newly generated output files in the new project hierarchy:


7) Open the original project and select the GT XCI to recustomize. You should now see that the ref clk has updated to the correct frequency.



AR# 66941
Date 04/25/2016
Status Active
Type General Article
  • Kintex UltraScale
  • Virtex UltraScale
  • Vivado Design Suite
  • XAUI