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AR# 66944

Design Advisory for Zynq UltraScale+ MPSoC - Updated package pinouts relative to Xilinx.com since April 5th, 2016

Description

Zynq UltraScale+ MPSoC package pinouts have changed relative to those recently available on Xilinx.com.

Solution

CSV Pinout Files:

  • Public Zynq UltraScale+ files have been updated on Xilinx.com as of 4/5/2016.

Zynq UltraScale+ Packages affected:

xczu11egffvb1517 (1)

xczu11egffvc1760 (1) (2)

xczu11egffvf1517 (1) (3)

xczu17egffvb1517 (1)

xczu17egffvc1760 (1)

xczu17egffvd1760 (1)

xczu17egffve1924 (1)

xczu19egffvb1517 (1)

xczu19egffvc1760 (1)

xczu19egffvd1760 (1)

xczu19egffve1924 (1)

xczu2egsbva484 (1) (4)

xczu2egsfva625 (2)

xczu2egsfvc784 (1) (2) (3) (4) (5)

xczu3egsfva625 (2)

xczu3egsfvc784 (1) (2) (3) (4) (5)

Pin difference key:

  • (1) SelectIO
  • (2) Supply
  • (3) GT
  • (4) PS MIO
  • (5) Dedicated/Config

Zynq UltraScale+ Packages Not Affected:

xczu9egffvb1156

xczu9egffvc900

xczu15egffvb1156

xczu15egffvc900

xczu6egffvb1156

xczu6egffvc900

A difference comparison of the Zynq UltraScale+ affected devices is attached to this Answer Record.

Attachments

Associated Attachments

Name File Size File Type
AR66944_csv_diff.zip 21 KB ZIP

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
66071 Design Advisory Master Answer Record for Zynq UltraScale+ MPSoC Devices N/A N/A
AR# 66944
Date Created 04/01/2016
Last Updated 08/23/2016
Status Active
Type Design Advisory
Devices
  • Zynq UltraScale+ MPSoC
Tools
  • Vivado Design Suite - 2016.1
  • Vivado Design Suite - 2015.4
  • Vivado Design Suite - 2016.2