AR# 66963


Design Advisory for Aurora 8B10B v11.0 Rev2 or later - Artix-7 GTP - Channel-up toggles periodically for Verilog IP


With Aurora 8B10B v11.0 Rev2 or later IP generated for Artix-7 GTP, channel-up is observed to be toggling periodically and does not achieve stable channel_up assertion.

This issue is observed with all Aurora 8B10B configurations when the IP is generated in Verilog. 

IP generated in VHDL is not impacted by this issue. This answer record provides the work-around to resolve this issue.


Root cause:

Due to floating connection to the RXRESETDONE port, rx_startup_fsm is stuck in the WAIT_RESET_DONE state. 

This initiates periodic reset due to timeout. This failure is seen in simulations when run for a very long time, and on hardware.

In the <core_name>_transceiver_wrapper.v file, the RXRESETDONE port of the <core_name>_rx_startup_fsm module instance is driven by rxfsm_rxresetdone_r1. 

This signal does not have a driver. The following snapshot shows the connectivity of the RXRESETDONE port with the <core_name>_rx_startup_fsm module instance.



To resolve this issue, make the following update in the <core_name>_rx_startup_fsm module instantiation in the <core_name>_wrapper.v file. 

Please refer to the code snippet below for the required edits:

Update from:

.RXRESETDONE                    (rxfsm_rxresetdone_r1),

Update to:

.RXRESETDONE                    (rxfsm_rxresetdone_r),


All of the Aurora 8B10B based designs targeting Artix-7 MUST be updated if the following conditions are met.

  1. Aurora 8B10B IP is generated from Vivado 2015.3 or later
  2. Aurora 8B10B IP is generated in Verilog

Designs in production which use the Aurora 8B10B IP from Vivado 2015.2 or earlier are not impacted. This issue will be fixed in Vivado 2016.2.

Revision History:

05/02/2016 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
51553 Design Advisory Master Answer Record for LogiCORE IP Aurora 8B10B and Aurora 64B66B N/A N/A
AR# 66963
Date 05/05/2016
Status Active
Type Design Advisory
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