2. Support
  3. AR# 6698: LogiCORE PCI - Why does the top-level PCI wrapper instantiate the PCI core wrapper instead of the core itself?
  4. AR# 66989: LogiCORE Video PHY Controller v2.0 - Why do I get a Critical Warning on GT placement when multiple Video PHY Controllers are used in my project?

AR# 66989

LogiCORE Video PHY Controller v2.0 - Why do I get a Critical Warning on GT placement when multiple Video PHY Controllers are used in my project?

Description

Why do I encounter the following Critical Warning in implementation if there are multiple Video PHY Controllers in my HDMI project?

This can happen in 1 of 2 use cases:

  1. The design has two Block Designs that each contain a Video PHY Controller.
  2. The design has a single Block Design that contains multiple Video PHY Controllers.


The issue does not occur if only one Video PHY is used.

Below are the two possible errors related to this issue which might be seen:

[Vivado 12-2285] Cannot set LOC property of instance 'hdmi_ch1/ch1_hdmi_x0y8_i/vid_phy_controller_1/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe3_top.ch2_x0y12_hdmi_vid_phy_controller_1_0_gtwrapper_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[3].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST', Instance hdmi_ch1/ch1_hdmi_x0y8_i/vid_phy_controller_1/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe3_top.ch2_x0y12_hdmi_vid_phy_controller_1_0_gtwrapper_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[3].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST can not be placed in GTHE3_CHANNEL of site GTHE3_CHANNEL_X0Y12 because the bel is occupied by hdmi_ch2/ch2_x0y12_hdmi_i/vid_phy_controller_1/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe3_top.ch2_x0y12_hdmi_vid_phy_controller_1_0_gtwrapper_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[3].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST. This could be caused by bel constraint conflict ["demo.srcs/sources_1/bd/ch2_x0y12_hdmi/ip/ch2_x0y12_hdmi_vid_phy_controller_1_0/ip_0/synth/ch2_x0y12_hdmi_vid_phy_controller_1_0_gtwrapper.xdc":57]

[filemgmt 20-1741] File 'vid_phy_controller_v2_0_2.v' is used by one or more modules, but with different contents, and may lead to unpredictable results: * <project_name>/demo.srcs/sources_1/bd/design_2/ip/design_2_vid_phy_controller_0_0/synth)

Solution

This is a known issue in Vivado 2015.4, 2016.1 and 2016.2. It will be fixed in the 2016.3 version of the Video PHY Controller.

The problem is that the Video PHY Controller always generates the same module name (vid_phy_v2_0_0.v) when wrapping the GT wizard instance.

This causes a conflict if there are multiple Video PHY controller blocks, and the first vid_phy_v2_0_0.v overwrites the others.

To work around this issue, use the following methods to avoid conflicts during global Synthesis:

  1. When the design has two Block Designs that each contain a Video PHY Controller, you can work around this by using the following methods:
    • Set the Block Design Synthesis Option to: Out Of Context (OOC) per IP
    • Set the Block Design Synthesis Option to: Out Of Context (OOC) per Block Design
  2. When the design has a single Block Design that contains multiple Video PHY Controllers, you can use the following method:
    • Set the Block Design Synthesis Option to: Out Of Context (OOC) per IP

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
66537 LogiCORE Video PHY Controller v2.0 - How do I modify the output of the Video PHY for my design, if the output is encrypted when generating an HDMI PHY for the 7 Series GTX? N/A N/A
54546 HDMI 1.4/2.0 Receiver (RX) Subsystem - Release Notes and Known Issues for the Vivado 2015.1 tool and later versions N/A N/A
65911 HDMI 1.4/2.0 Transmitter (TX) Subsystem - Release Notes and Known Issues for the Vivado 2015.4 tool and later versions N/A N/A
AR# 66989
Date 09/12/2016
Status Active
Type General Article
IP