AR# 67004

Vivado Constraints - Constraints Scoping Master Answer Record


Vivado Tool supports Scoped Constraints feature which is to associate an XDC file to a subset of a design, such as a submodule netlist, different portions of the design in Team Design Flow, an IP in the design.

This Answer Record provides information and common issues regarding Constraints Scoping Methodology.


1) Documentations

Please refer to the following User Guides for Constraints Scoping Methodology.

(UG903) - Vivado Design Suite User Guide: Using Constraints
  • Chapter 2 -> Constraints Scoping
(UG896) - Vivado Design Suite User Guide: Designing with IP
  • Chapter 2 -> Managing IP Constraints
2) Constraints Methodology when using DCP.

(Xilinx Answer 66987) Vivado Constraints - Useful things to know about Constraint Scoping methodology when using post-synthesis OOC DCP

3) Common Issues in Constraints Scoping Methodology.

(Xilinx Answer 63960) FIFO Generator v12.0 - [Common 17-55] 'get_property' expects at least one object.[axis_fifo_32x16_clocks.xdc]
(Xilinx Answer 56169) Vivado Constraints - CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object
(Xilinx Answer 58308) Vivado Constraints - FIFO Generator IP constraints get inadvertently dropped
(Xilinx Answer 58260) Vivado Constraints - "WARNING: [Vivado 12-584] No ports matched..." occurs on I/O placement constraints for IP
(Xilinx Answer 59799) Vivado Constraints - How to avoid overwriting clock constraints when using create_clock constraints in scoped constraint files?
(Xilinx Answer 54799) Vivado Synthesis - Warnings/Critical Warnings related to XDC constraints seen in Synthesis but not in Implementation
AR# 67004
Date 08/08/2017
Status Active
Type General Article