When using the 7 Series Integrated Block for PCI Express core example design in Vivado 2013.4, incorrect behavior is seen with completion being sent out when s_axis_tx_tready is not continuously asserted.
This article is part of the PCI Express Solution Centre
|(Xilinx Answer 34536)||Xilinx Solution Center for PCI Express|
This is a known issue with the example design logic. This has been fixed in Vivado 2014.2.
To work around this issue, replace the following code:
Replace it with this code: