Version Found: DDR4 v2.0
Version Resolved: See (Xilinx Answer 69035)
A DDR4 design with DBI Read enabled results in the Read Complex registers not being populated in the XSDB BRAM.
Within the Hardware Manager MIG Debug GUI, a margin bar for only the first nibble will be displayed. The other nibbles will be empty.
When DBI Read is Disabled, these registers are populated properly and visible within the Hardware Manager Debug GUI.
These registers cannot be used when Read DBI is enabled. The Simple Read window can be used as an estimate or to find the approximate Read Complex window.
A core without Read DBI enabled can be run in hardware until this issue is resolved.
04/15/16 - Initial Release