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AR# 67008

DDR4 UltraScale - Enabling DBI Read causes Read Complex register values in XSDB BRAM to not be populated

Description

Version Found: v2.0

Version Resolved: See (Xilinx Answer 58435)

A DDR4 design with DBI Read enabled results in the Read Complex registers not being populated in the XSDB BRAM. Within the Hardware Manager MIG Debug GUI, a margin bar for only the first nibble will be displayed. The other nibbles will be empty.

When DBI Read is Disabled, these registers are populated properly and visible within the Hardware Manager Debug GUI.

Solution

These registers cannot be used when Read DBI is enabled. The Simple Read window can be used as an estimate or to find the approximate Read Complex window. 

A core without Read DBI enabled can be run in hardware until this issue is resolved.

Revision History:

04/15/16 - Initial Release

AR# 67008
Date Created 04/11/2016
Last Updated 04/21/2016
Status Active
Type Known Issues
Devices
  • Kintex UltraScale
  • Virtex UltraScale
IP
  • MIG UltraScale