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AR# 67008

UltraScale DDR4 - Enabling DBI Read causes Read Complex register values in XSDB BRAM to not be populated


Version Found: DDR4 v2.0

Version Resolved: See (Xilinx Answer 69035)

A DDR4 design with DBI Read enabled results in the Read Complex registers not being populated in the XSDB BRAM. 

Within the Hardware Manager MIG Debug GUI, a margin bar for only the first nibble will be displayed. The other nibbles will be empty.

When DBI Read is Disabled, these registers are populated properly and visible within the Hardware Manager Debug GUI.


These registers cannot be used when Read DBI is enabled. The Simple Read window can be used as an estimate or to find the approximate Read Complex window.

A core without Read DBI enabled can be run in hardware until this issue is resolved.

Revision History:

04/15/16 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
69035 UltraScale/UltraScale+ DDR4 - Release Notes and Known Issues N/A N/A
AR# 67008
Date 01/02/2018
Status Active
Type Known Issues
  • Kintex UltraScale
  • Virtex UltraScale
  • Vivado Design Suite - 2016.1
  • Vivado Design Suite - 2016.2
  • Vivado Design Suite - 2016.3
  • MIG UltraScale
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