We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 6701

VERILOG-XL - How do I run simulation with Verilog-XL?


Keywords: Verilog-XL, Unisims, Simprims, verilog, simulation

Urgency: Standard

General Description:
How do I run simulation with Verilog-XL?


Depending on the makeup of the design (LogiBLOX, Xilinx instantiated
primitives, or Coregen components), for RTL simulation, specify the
following at the command-line:

verilog -y $XILINX/verilog/src/unisims -y $XILINX/verilog/src/simprims \
+incdir+$XILINX/verilog/src +libext+.v $XILINX/verilog/src/glbl.v \
<testfixture>.v <design>.v

The $XILINX/verilog/src/unisims area contains the Unified components
for RTL simulation. The $XILINX/verilog/src/simprims area contains
generic simulation primitives for LogiBLOX.

For timing simulation or post-Ngd2ver, the Simprims-based libraries are
used. Specify the following at the command-line:

verilog -y $XILINX/verilog/src/simprims $XILINX/verilog/src/glbl.v \
+libext+.v <testfixture>.v <design>.v

Please see (Xilinx Solution 3167) on how to specify the Xilinx
SimPrim library path using the NGD2VER-ul command-line switch
instead of using the Verilog-XL -y command-line switch.
AR# 6701
Date Created 06/07/1999
Last Updated 05/05/2004
Status Archive
Type General Article