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AR# 67020

2016.1 - Zynq UltraScale - Trace port mapping incorrect in Zynq UltraScale GUI

Description

If I enable the Trace port in the Zynq UltraScale GUI in IP Integrator, the Trace port's mappings are incorrect.

How can I work around this?

Solution

This is a bug in Vivado 2016.1.

To work around this issue, download the patch attached to this Answer Record, and following the steps in the patch_readme.

Attachments

Associated Attachments

Name File Size File Type
AR67020_vivado_2016_1_preliminary_rev1.zip 3 MB ZIP
AR# 67020
Date Created 04/12/2016
Last Updated 04/22/2016
Status Active
Type General Article
Devices
  • Zynq UltraScale+ MPSoC
Tools
  • Vivado Design Suite - 2016.1
IP
  • Zynq UltraScale+ MPSoC Processing System