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AR# 67044

JESD204 PHY v2.0, v3.0, v3.1 (2015.1, 2015.2, 2015.3, 2015.4, 2016.1) - TXDIFFCTRL low default value


When using the JESD204 PHY core, if the optional setting "AXI4-Lite Management Interface" is selected then the TXDIFFCTRL register defaults to 4'b0000. This corresponds to a very low amplitude which is unlikely to be suitable in the majority of applications. 

It is recommended that the value 4'b1000 be programmed unless changes in the TX amplitude are recommended by Xilinx, or you understand the implications of altering the transmit drive strength. 

The default when the "AXI4-Lite Management interface" option is not selected is 4'b1000.

When using the JESD204 v7.0 core with the setting "Include Shared Logic in the core" selected, the TXDIFFCTRL default value is 4'b1000.


Program the value 0x8 into register 0x508 for every TX transceiver channel.

Note that register 0x024 selects the transceiver control register bank to be accessed and should be programmed before writing to register 0x508.

For example: 

To program all of the transceivers of a JESD204 PHY core containing four lanes to the correct default value, the following register writes must be performed (assuming the JESD204 PHY is at a base address of 0x100000):

wr 0x0 to 0x100024 // Select GT channel 0
wr 0x8 to 0x100508 // Set TXDIFFCTRL to 4'b1000
wr 0x1 to 0x100024 // Select GT channel 1
wr 0x8 to 0x100508 // Set TXDIFFCTRL to 4'b1000
wr 0x2 to 0x100024 // Select GT channel 2
wr 0x8 to 0x100508 // Set TXDIFFCTRL to 4'b1000
wr 0x3 to 0x100024 // Select GT channel 3
wr 0x8 to 0x100508 // Set TXDIFFCTRL to 4'b1000

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
61911 LogiCORE IP JESD204 PHY core - Release Notes and Known Issues N/A N/A
AR# 67044
Date 05/27/2016
Status Active
Type General Article
  • JESD204
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