When using the JESD204 PHY core, if the optional setting "AXI4-Lite Management Interface" is selected then the TXDIFFCTRL register defaults to 4'b0000. This corresponds to a very low amplitude which is unlikely to be suitable in the majority of applications.
It is recommended that the value 4'b1000 be programmed unless changes in the TX amplitude are recommended by Xilinx, or you understand the implications of altering the transmit drive strength.
The default when the "AXI4-Lite Management interface" option is not selected is 4'b1000.
When using the JESD204 v7.0 core with the setting "Include Shared Logic in the core" selected, the TXDIFFCTRL default value is 4'b1000.
Program the value 0x8 into register 0x508 for every TX transceiver channel.
Note that register 0x024 selects the transceiver control register bank to be accessed and should be programmed before writing to register 0x508.
To program all of the transceivers of a JESD204 PHY core containing four lanes to the correct default value, the following register writes must be performed (assuming the JESD204 PHY is at a base address of 0x100000):