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AR# 67062

Zynq - Can the output signals of a Zynq-7000 PS peripheral (such as GigE, SD, etc) be probed by an ILA when mapped to PS I/O pins through MIO (FIXED_IO bus)?


Is it possible to connect an ILA core to the signals comingfrom or going to the peripherals on the Zynq PS7 if the output is routed to themultiplexed I/O pins (MIO or FIXED_IO) so that the output or bidirectionaltraffic can be analyzed?


Because the ILA and VIO cores reside in the Zynq PL (fabric), the output signals from the peripheral must have a routing path from the peripheral onto the fabric.


If the peripheral is mapped to the multiplexed I/O pins (MIO) then there is no path for these signals to get to the fabric and to be probed by an ILA or VIO which reside in the PL.

The tools will allow the MIO or FIXED_IO to have MARK_DEBUG set TRUE, however they will issue the warning below during synthesis:

[Chipscope 16-3] Cannot debug net 'design_1_i/MIO[0]'; it is not accessible from the fabric routing.

These signals can be probed by an ILA or VIO core if the output is moved from the MIO bus to the EMIO bus which allows a path to the PL fabric, however the peripheral's output will no longer route to the MIO pin.

This requires a pinout change, as the signals will pass through the fabric and can be probed on the way to a SelectIO pin accessible from the PL.

The paths to either MIO or EMIO are shown below in figure 2-3 from the Zynq-7000 TRM (UG585):



AR# 67062
Date 05/18/2018
Status Active
Type General Article
  • Zynq-7000
  • XA Zynq-7000
  • Zynq-7000Q
  • Vivado Design Suite
  • Integrated Logic Analyzer
  • Virtual Input/Output (VIO)
  • ChipScope VIO
  • ChipScope ILA
Boards & Kits
  • Zynq-7000 SoC Boards and Kits
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