We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 6709

FPGA Configuration - Done pin does not go high, Startup block is used


Device seems to complete configuration, but startup sequence is not completed. Done pin does not go high.


The following are configuration problems relating to the use of the Startup primitive.

Older versions of BitGen set startupclk=userclk

When you connect the Clk pin of the Startup primitive to Ground, BitGen recognizes that the Startup Clk is used (it does not recognize that it is a Ground) and uses the Ground as the clock for startup. This is why the Done pin never goes high. You can regenerate the bitstream with the "-g StartupClk:CCLK" option in BitGen. For more details see (Xilinx Answer 4681).

Connecting GTS to an external pin

When you connect the GTS pin on the Startup primitive to a user I/O, you may encounter configuration problems. The device can get stuck in the startup sequence if the pre-configuration pullups are enabled on the I/Os. The pre-configuration pullups cause the GTS input on the Startup primitive to be enabled. The GTS signal will never deactivate, and causes the startup sequence to get stuck in the cycle where it waits for GTS to release.

You can work around this problem in a few ways:

a. (preferred) Do not connect the GTS input on the Startup primitive to an external source.

b. Enable pre-configuration pulldowns instead of pre-configuration pullups:

- For Virtex/-E and Spartan-II/-E, this is done by changing the MODE pins.

- For Virtex-II/-II Pro and Spartan-3, this is done with the HSWAP_EN pin.

AR# 6709
Date 02/17/2013
Status Active
Type General Article