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AR# 67098

2016.1 UltraScale Implementation - New DRC check for clock routing in UltraScale results in both new positive and false-positive errors.


A new DRC check has been added in Vivado 2016.1 that enforces a limit of six global clocks per half I/O bank, as that is the number of clock spines available. 

However, a case has been seen where a false positive was flagged related to BUFG_GT clocks.

[Place 30-912] Bank 65 has 7 different clocks driving IO loads in the top half. There can only be a maximum of 6 clocks in any half of an IO bank. The list of clock source instances driving IO loads in this half of the bank is as follows:


If an existing design had routed successfully in previous revisions but fails in Vivado 2016.1, then one of two possibilities is occurring:

  1. The design has an over subscribed half I/O bank and was routing previously with non-optimal clock routing that used local fabric resources. In this case I/O utilization or clocking should be reconsidered.
  2. A false positive has occurred, possibly involving BUFG_GT clocks and the implementation is actually correct. In this case the check should be disabled.

The difference between these two conditions can be determined by examining the timing of the clock nets driven by the clock buffers listed in the error message and/or checking the placement of the loads of those nets to see if they actually have loads in the I/O column of the bank in question.

The false DRC checks can be disabled by setting the following parameters before running implementation:

set_param place.enablePrePlaceDrcChecks false
set_param route.noDrc true

Note: Disabling DRC for placement and routing is something that should only be done when necessary. Any real errors will still be caught at bit file generation, but would be caught sooner with DRC enabled.

The false DRC errors are scheduled to be fixed for Vivado 2016.2.

AR# 67098
Date 04/28/2016
Status Active
Type General Article
  • Virtex UltraScale
  • Kintex UltraScale
  • Vivado Design Suite - 2016.1