How is the VADJ rail treated on UltraScale Boards and Kits?
For UltraScale Boards and Kits, the process for VADJ read as defined in VITA57.1 FMC specification is followed.
This involves the querying of the Mezzanine Card's EPROM to ensure that the VADJ voltage is brought up at the correct voltage.
The Maxim Integrated power controllers on the UltraScale Boards and Kits power on with VADJ off by design.
VADJ gets enabled by the MSP430 System Controller after power-on under the following conditions (1 or 2 or 3):
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
63175 | Kintex UltraScale FPGA KCU105 Evaluation Kit - Known Issues and Release Notes Master Answer Record | N/A | N/A |
62603 | Virtex UltraScale FPGA VCU108 Evaluation Kit - Known Issues and Release Notes Master Answer Record | N/A | N/A |
62604 | Virtex UltraScale FPGA VCU110 Evaluation Kit - Known Issues and Release Notes Master Answer Record | N/A | N/A |
66752 | Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit - Known Issues and Release Notes Master Answer Record | N/A | N/A |