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AR# 67142

2016.1 - Simulation - Project Utilities Tcl App update required for Export Simulation


When using Export Simulation to generate simulation scripts in Vivado 2016.1, I receive errors and/or the scripts are created improperly.

For example, irun fails for a non-System Verilog compliant design due to global scope being set with the sv switch on irun:

irun: *E,VLGERR: An error occurred during parsing. Review the log file for errors with the code *E and fix those identified problems to proceed. Exiting with code (status 1).

ncvlog: *E,FNDKWD (../../../project_wave_gen/project_wave_gen.srcs/sim_1/imports/tb/tb_cmd_gen.v,202|19): A SystemVerilog keyword was found where an identifier was expected.

input [15:0] val

Another example is confusion around design unit binding when -lib_map_path is passed to the generated simulation script.

ncelab: W,MISSYST: Unrecognized system task or function: {*Name Protected} (did not match built-in or user-defined names) [2.7.4(IEEE Std 1364-2001)].

If item was defined in a shared-object library, the problem could be:

libvpi.so: cannot open shared object file: No such file or directory or file is not valid ELFCLASS64 library.

libpli.so: cannot open shared object file: No such file or directory or file is not valid ELFCLASS64 library..

ncelab: *E,MULVLG: Possible bindings for instance of design unit 'SRLC32E' in 'axi_data_fifo_v2_1_7.axi_data_fifo_v2_1_7_ndeep_srl:v' are: 



Is there a work-around for this limitation?


The current work-around is to update the Tcl App for Project Utilities within the Xilinx Tcl Store.

To do this please follow the steps below:

  1. Open Vivado 2016.1
  2. Click on Xilinx Tcl Store within the Task Window or find it in Tools > Xilinx Tcl Store.
  3. Refresh the Catalog.
  4. Install Revision 3.159 of Project Utilities.

You can now use Export Simulation to generate correct simulation scripts.

The fix will be integrated in Vivado 2016.2.

AR# 67142
Date 05/12/2016
Status Active
Type General Article
  • Vivado Design Suite - 2016.1